1. Field of the Invention
The present invention relates to a semiconductor fabrication process. More particularly, the present invention relates to a method of relieving wafer stress.
2. Description of the Related Art
At present, most semiconductor devices are fabricated on silicon wafers. To increase productivity and lower production cost, the diameter of wafers has been increased steadily from 4, 5, 6, 8 inches to 12 inches so that more chips can be fabricated from a single wafer.
In most semiconductor fabrication processes, a continuous film layer first deposited over a wafer before performing a photolithographic and etching process to pattern the film. For example, in the process of fabricating metallic interconnects, a dielectric layer is formed over a wafer and then patterned to form a via opening or a trench before depositing metallic material into the via opening or the trench. When the deposited film induces stress in the wafer due to some processing factors (such as a chemical-mechanical polishing operation), the entire wafer may warp. If such wafer stress is not relieved in time, subsequently processing operations is likely to be affected.
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for fabricating conventional metallic interconnects. First, as shown in FIG. 1A, a wafer 100 having a dielectric layer 102 with a plurality of contacts/vias 104 therein is provided. A dielectric layer 106 is formed over the entire wafer 100 to cover the dielectric layer 102 and the contacts/vias 104. Because the dielectric layer 106 may accumulate some internal stress, the wafer 100 is slightly warped.
As shown in FIG. 1B, a photolithographic process is carried out to form a patterned photoresist layer 108 over the dielectric layer 106. The patterned photoresist layer 108 exposes a portion of dielectric layer 106 where trenches are required. In other words, the photoresist layer 108 exposes the locations for forming the desired metallic lines.
As shown in FIG. 1C, the exposed dielectric layer 106 is etched to form a plurality of openings 110. Because the dielectric layer 106 is no longer a continuous sheet after removing a portion of the dielectric layer 106 to form the openings 110, internal stress is relieved so that the wafer returns to its former warp-free state.
In the aforementioned process, the patterned photoresist layer 108 is formed over a warped dielectric layer 106. Because the wafer 100 will return to its warp-free state as soon as the opening 110 is formed in the dielectric layer 106, the openings 110 may shift relative to the intended positions. As a result, misalignment of the contacts/vias 104 occurs quite frequently.
Furthermore, the misalignment problem aggravates from the warping center towards the edge of a wafer. Hence, the misalignment problem is particularly serious for a wafer with a larger diameter. For a chips lying in the peripheral region of a wafer, the situation may be so serious that the metallic interconnect process fails to link up a metallic line with a corresponding contact or via. When this happens, performance of the device will deteriorate and yield of the chip will drop.